Fabless-ASIC company tries new model
By Ron Wilson, Executive Editor -- EDN, 5/11/2006
Maybe the world isn't beating the bushes to find another fabless-ASIC company. But start-up Key ASIC believes that it has a model—an application-specific approach—that's just different enough to make a place for itself beside the relative giants, such as eSilicon (www.esilicon.com) and Open-Silicon (www.open-silicon.com). The company drew its digital engineers from hardware-optimization company Arcadia Design Systems and its mixed-signal engineers from Intel (www.intel.com). Key ASIC now has two design teams comprising 30 engineers. Half of the members are in Silicon Valley, and half are in Malaysia. Working with a number of independent IP (intellectual-property) companies, the company has built up a portfolio that includes an ARM9 core, high-speed interface IP, audio and video—including HD—ADCs, and power-conversion blocks. The company targets the consumer and wireless-device markets.
The ARM9 illustrates the value added in Key ASIC's approach. Rather than simply pass a synthesizable core through to customers, the company uses customer specs to produce an optimized hard core with the speed, power, and cache configuration the customer needs. Presumably, the company will take a similar approach to the other critical datapaths in the customer's SOC (system-on-chip) design.
Key ASIC offers two-month turnaround on multidesign wafer-shuttle services, as well as full concept-to-production joint design with the customer. With its roots in Malaysia, the company has insider knowledge of the packaging, testing, and yield-engineering portions of the process. Key ASIC is currently offering 180- and 130-nm CMOS processes from SilTerra (www.silterra.com) and TSMC (www.tsmc.com). Initial customer designs and some of the IP blocks are currently in shuttle runs, and the company expects to have production tape-outs this year.