Senior/Staff Place and Route Engineer

  • Senior/Staff Place and Route Engineer

Job Description:

In this position, you will be responsible for physical design implementation. Your scope of work includes but not limited to
• Create optimum floor plan that able to meet design specs with smallest possible die size
• Full-chip and block level power planning, IR drop and EM analysis
• Collaterals (lib, lef, milkyway database and etc) preparation for place and route
• Full-chip and block level place and route, and Chip integration
• Perform clock tree synthesis to achieve balanced clock for all functional and test modes
• RC extraction 
• LVS/DRC verification and fixes
• Functional and timing ECO implementation
• IR-drop (static and dynamic) and EM analysis
• Develop P&R methodology to improve design efficiency and productivity
• Perform tapeout checklist on the physical implementation aspects of the design
• Familiar with low power and hierarchical design implementations

http://www.keyasic.com/images/icon01.gif) 10px 15px no-repeat rgb(245, 238, 255);">Limited Requirement

DEGREE:
BS/MS in Electrical/Electronics/Computing Engineering required. Previous experience in P&R design is a must. Advanced degree in an engineering discipline is a plus.
Other Requirement:
The ideal candidate should have a minimum 5-8 years of experience in related field for staff level, and at least 3 years for senior level. 
The candidate should be knowledgeable in physical design with hands-on experience in the full-chip/block level placement and route, floor planning, power planning, chip integration, supporting Engineering Change Order (ECO), timing closure, power and clock optimization, and physical verification. The candidate needs to be able to work on the entire gamut of the P&R independently. In addition to that, he/she needs to have exposure in all aspects of the ASIC design flow. Knowledge in RTL synthesis, DFT, gate-level simulation, static timing analysis and timing convergence skills is a plus. Hands-on experience in advanced chip design with deep sub-micron technology (65nm and below) is a must. Problem solving capability in low power design, hierarchical design, signal integrity and cross coupling noise is required. The ability to work with and develop relationships with multiple function groups and execute in a fast paced environment is essential. 
We are looking for independent, energetic, dynamic, proactive and responsible person to fill this position. For staff level position, the candidate is required to have working experience in leading role, and portray strong interpersonal, leadership and management skills
Post Date:2014-10-27