Physical Design Lead

  • Physical Design Lead

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Job Description:

In this position, you will be responsible to lead and to manage an implementation team. Your scope of work includes but not limited to
• Team development roadmap
• Projects and resource management
• Define objectives and working plan, and determine modes of resource deployment in order to meet schedule for various projects
• Lead a team to go through the whole physical implementation flows which includes: collaterals preparation, sanity checks on incoming collaterals, RTL synthesis, floor planning, place and route, STA, timing convergence, DFT, IR-drop, EM, gate-level simulation, verification and etc
• Project status and schedule tracking
• Outgoing design/database quality check
• Chair and drive tape out reviews and sign-off checklist
• Manage customer expectations
• Support tape out process and post-silicon debug activities
• Coordinate the communications between front end team/customers, foundries, IP providers, production team and marketing teams

Limited Requirement

DEGREE:
BS/MS Electrical Engineering from a reputable univerBS/MS in Electrical/Electronics/Computing Engineering required. Previous experience in ASIC backend leading role is required. Advanced degree in an engineering discipline is a plus.
Other Requirement:
The ideal candidate should have a minimum 8-10 years of experience in related field. 
We are looking for independent, energetic, dynamic, proactive, positive and responsible person to fill this position. He/she is required to have working experience in leading role, and portray strong interpersonal, communication, leadership and management skills. 
The candidate should have strong knowledge in the full suite of ASIC physical design flows. Hands-on experience in advanced chip design with deep sub-micron technology (65nm and below) is a must. Deep understanding of the EDA tools (Synopsys, Cadence, Mentor Graphics) is a must. Hands on experience in low power design flow (UPF/CPF) and hierarchical design flow are a must. Knowledge of Verilog/VHDL hardware description language at moderate level is required. 

 

Post Date:2014-10-27