SENIOR P&R DESIGN ENGINEERS

Job Description

In this position, you will be responsible for physical design implementation. Your scope of work includes but not limited to

• Create optimum floor plan that able to meet design specs with smaller die size.
• Power planning and IR drop analysis
• Collateral preparation for P&R
• LVS/DRC verification and fixes
• Chip integration and P&R
• ECO routing and physical optimization
• Develop P&R methodology to improve design efficiency and productivity.
• RC extraction
• CTS and timing optimization
• Custom layout editing

In this highly challenging design role, the P&R lead designer is to work with a team for the development of CPU and SoC design in 0.18 um, 0.13 um, 90nm and below technologies. Driven by high performance and low power design requirements, you need to work closely with other engineering teams and product marketing teams for end product development. Understanding of the application of the ARM cores in various domains is a plus, system SOC integration and interface needs to be continuously strengthened.

Qualifications

The ideal candidate should be knowledgeable in physical design with hands-on experience in the Block Placement and Route, Floor Planning, Chip Integration and Place & Route, Engineering Change Order (ECO), Timing Closure, Power and Clock Optimization, and Physical Verification. The candidate needs to be able to work on the entire gamut of the P&R independently. In addition to that one needs to participate in all aspects of the design flow. Hands-on experience in advanced chip design with deep sub-micron technology is a must. Power planning and optimization is critical for consumer and communication IC chips. Problem solving capability in low power design, signal integrity and cross coupling is required. The ability to work with and develop relationships with multiple function groups and execute in a fast paced environment is essential.

Required Education:
Previous experience in P&R design is required. Advanced degree in an engineering discipline is preferred.