(Kuala Lumpur, March 24, 2026)

In the current semiconductor landscape, headlines are dominated by core counts, TOPS (Trillions of Operations Per Second), and very large bandwidths. However, hidden beneath the logic gates and HBM stacks lies a fundamental component that dictates the stability of the entire system: the Phase-Locked Loop (PLL).

As we transition into the era of PCIe Gen 6, 112G SerDes, and multi-die chiplet architectures, the margin for error in timing has all but vanished. The "Unit Interval" (UI)—the very small window of time available to transmit or receive a bit of data—is shrinking to picosecond levels. In this environment, the clock source is no longer just a heartbeat; it is the structural foundation of signal integrity.

At Key ASIC, our engineering teams are observing a critical inflection point. The traditional clocking architectures that served the industry well for the past decade are hitting a physical wall. To support the data rates of 64Gbps and beyond, we believe a fundamental architectural shift is necessary.

This article outlines our R&D team's upcoming PLL suitable for high-speed SerDes having ultra low jitter with LC- tank VCO, and supporting up to 16 GHz output clock to sample the data.

The Problem: When Physics Fights Back

For years, Ring Oscillator (RO) based PLLs were a good choice for a long bandwidth PLL with area budget but not good for very precise jitter. They are compact, scalable across process nodes, and offer wide tuning ranges. However, as frequency demands push past 10 GHz, the physics of Ring Oscillators becomes a liability.

Ring Oscillators rely on the delay of cascaded inverters. At high frequencies, maintaining a clean spectral output becomes exponentially difficult due to their inherent low quality factor (Q-factor). They are susceptible to thermal noise and, more critically, power supply noise. In a noisy, high-current and supply ripples RO translate into more phase noise (Jitter) to its output clock and make the eye worse in data-rate sampling of the high-speed SerDes.

When targeting next-generation applications requiring <800 femtoseconds (fs) of RMS jitter, the Ring Oscillator simply runs out of headroom. To break this barrier, we must move from a structure that is "flexible" to one that is "resonant."

The Solution: Returning to First Principles with LC-Tank Topologies

Key ASIC’s next-generation IP roadmap is centered around the low jitter PLL for high-speed SerDes to move over it we are using LC-Core to oscillate over 2GHz output clock of the Jitter. (LC-VCOs).

Unlike the noisy delay chain of a Ring Oscillator, an LC-tank utilizes an on-chip inductor (L) and a capacitor (C) to create a resonant circuit. This structure provides a significantly higher Q-factor. Imagine the difference between a rubber band (Ring Osc) and a tuning fork (LC-Tank). The tuning fork resists external disturbances and vibrates at a pure, singular tone.

Our ongoing architectural simulations target a jitter budget where the LC-VCO contribution is suppressed to under 400 fs. This establishes a "noise floor" that is physically impossible to achieve with traditional RO designs at equivalent power levels in this frequency band.

However, implementing LC-tanks in modern CMOS processes is not without challenges. Inductors consume silicon area, and their tuning range is narrower. Our R&D focus is currently solving the "tuning range vs. phase noise" trade-off, developing switched-capacitor banks and output divider that allow the PLL to cover the broad 2–16 GHz spectrum without sacrificing the purity of the resonance.

The Dual-Path Charge Pump Concept

While the LC-VCO sets the noise floor, the Charge Pump (CP) often introduces the "spikes" seen in a spectrum analyzer. In high-speed PLLs, current mismatch between the "UP" and "DOWN" currents in the charge pump creates reference spurs. These spurs are disastrous for ADC/DAC clocking and high-speed SerDes, as they manifest as deterministic jitter (DJ).

Key ASIC is currently developing a novel Dual-Path Charge Pump architecture to address this.

Standard designs often struggle to maintain current matching across Process, Voltage, and Temperature (PVT) variations. Our developing architecture introduces a "Replica Path" concept. While the primary path drives the loop filter for frequency acquisition, the secondary path works to maintain continuous charge balance.

The design target is reducing the mismatch between the UP and DOWN currents and resulting in minimize the spurs. So, the contribution in to the noise of the VCO is reduced which makes the PLL more suitable for our targeted specifications. Furthermore, we are using the Charge Pump with a wide programmable current range (targeting 20µA to 320µA) by using multiple stages with control circuitry. This programmability is crucial for SoC architects, allowing them to dynamically adjust the loop bandwidth—optimizing for fast locking during wake-up sequences or maximum jitter rejection during steady-state data transmission.

Noise Immunity

A PLL does not exist in a vacuum. It lives on a silicon die surrounded by billions of noisy, switching and current carrying transistors. A lab-perfect PLL can fail miserably in a real chip if it lacks immunity to Power Supply Noise (PSN).

Our design philosophy for this new IP places heavy emphasis on Power Supply Rejection Ratio (PSRR). We are simulating the architecture against aggressive noise profiles typical of high-performance computing environments.

The architectural goal includes:

• Deep-Submicron Regulators: Integrated LDOs specifically tuned to filter out switching noise frequencies.
• Optimized Loop Filters: Designing the multiple order passive loop filter to provide >80 dB of attenuation at critical offset frequencies (e.g., 1 MHz), creating a "spectral quiet zone" where it matters most.

Target Specifications & Application Relevance

While this IP is currently in the active development phase, our design targets are set to meet the rigorous demands of the next 5 years of computing:

• Output Frequency Range: 2 GHz to 16 GHz (Continuous coverage via capacitor banking and output Divider)
• Jitter Target: < 500 fs RMS (Integrated from 10kHz to 100MHz)
• Locking Time Target: < 100 µs (To support aggressive power-gating strategies)

These specifications are not random; they are derived from the requirements of 32G/56G SerDes, Precision ADC clocking, and AI Die-to-Die interconnects. By targeting these specs, we aim to provide a clocking foundation that allows our partners to utilize the full bandwidth of their interfaces without being bottlenecked by timing uncertainty.

Collaborating on the Future

Key ASIC believes that the best IP is built in collaboration with the architects who will use it.

As we move from architectural exploration to circuit design and eventual silicon validation, we are opening conversations with lead partners. We invite system architects and SoC leads to discuss their specific clocking challenges with us.

• Are you struggling with Ring Oscillator noise in your current designs?
• Does your roadmap call for tighter jitter budgets that your current IP library cannot support?

By sharing your requirements early, you can help influence the final characterization and feature set of this cutting-edge PLL.

The move to Low jitter PLL architectures at 16GHz is not just an upgrade; it is a necessity for the high-speed data era. Key ASIC is committed to solving the hard physical problems of timing, ensuring that when your next-generation chip comes back from the fab, the heartbeat of your system is strong, stable, and ready for mass production.

【About Key ASIC】

Key ASIC, listed on Bursa Malaysia (0143), is one of the world's leading turnkey ASIC design service companies, offering comprehensive support from design to chip production.

• Over 100 ASIC designs in mass production
• 100% successful ASIC tape out
• Over 150 silicon-proven IPs (e.g., DDR, SerDes, PCIe, USB, Ethernet, etc.)

As a foundry-independent company, we collaborate with top-tier foundries worldwide, providing unparalleled flexibility and expertise to meet our customers' diverse needs.

Key ASIC is here to provide the best partnership for your ASIC business.

Please feel free to contact us via email: This email address is being protected from spambots. You need JavaScript enabled to view it.

Note: The technical specifications mentioned in this article represent current R&D design targets and are subject to change based on final silicon characterization.

(Kuala Lumpur, March 17, 2026)

In a modern System-on-Chip (SoC) design, engineers tend to focus on the headline features—NPUs, high-speed SerDes, and multi-core CPU clusters. These are the components that usually get all the attention. But the reliability of these billion-transistor systems often depends on a much simpler and frequently overlooked block: the Reset Controller.

An SoC is only as reliable as its ability to power up correctly and shut down safely. If a chip starts up in an undefined state because of a power glitch, or if it tries to write to flash memory while the voltage is dropping, the consequences can go far beyond a temporary error. You could end up with system crashes, corrupted data, or even a completely “bricked” device.

As process nodes continue to shrink and core voltages drop to around 0.8V, the margin for noise in logic levels has become extremely small. Traditional RC-based reset circuits simply don’t have the precision needed to reliably tell the difference between a normal power-up sequence and a risky voltage fluctuation.

That’s where Key ASIC’s Integrated Power-On Reset (POR) IP comes in. Designed for the harsh conditions of industrial environments and the tight precision required by low-voltage logic, this IP acts like a safety net—providing the dependable reset behavior that modern embedded systems need.

The Challenge: Designing for Uncertainty

Power is almost never perfect in real-world systems. In environments like industrial automation, automotive electronics, and battery-powered IoT devices, supply voltages tend to be noisy, clean monotonic ramps are uncommon, and dealing with “dirty power” is simply the norm.

SoC designers face two distinct but related challenges:

1. Startup Phase (The POR Challenge):

When power is first applied, the voltage ramps up from 0V to the target operating voltage. During this time, logic gates don’t behave predictably—they’re in an undefined state. If there isn’t a proper reset holding everything in place until the voltage stabilizes, flip-flops can capture random values. That can lead to the CPU running garbage instructions or buses fighting each other, which in the worst case can damage the chip before it even finishes booting.

2. Operational Phase (The BOR Challenge):

Even after the system is up and running, power issues can still cause trouble. A sudden heavy load—like a motor turning on or a wireless radio transmitting—can create a temporary voltage dip. If the core voltage falls below the minimum level needed to reliably hold logic states (for example, dropping from 0.8V to 0.6V), the CPU might start making incorrect calculations, or SRAM may lose stored data. If the system keeps running during this kind of brown-out condition, data corruption is almost inevitable.

Key ASIC’s IP integrates both of these protection mechanisms into a single compact, silicon-proven block, addressing power integrity issues during both startup and normal operation. 

Power-On Reset (POR)

The Key ASIC POR module basically acts as the system’s gatekeeper. It keeps an eye on the supply voltage as it ramps up, using precise analog monitoring.

Unlike simple digital designs that just wait for a certain number of clock cycles, our POR actually looks at the voltage itself. As soon as it detects power coming up, it immediately asserts the reset signal and keeps it active. It only releases the system from reset after the supply voltage passes a predefined threshold and has settled to a stable level.

Key Design Features:

• Glitch Immunity: In industrial power supplies, the startup voltage ramp is often a bit jagged rather than perfectly smooth. To handle that, our POR includes hysteresis and filtering. This helps prevent “stuttering,” where the reset signal rapidly releases and then asserts again, which can easily confuse state machines.
• Monotonicity Independence: Even if the power supply ramp pauses for a moment or doesn’t increase smoothly, the POR logic makes sure the system stays safely in reset. It only releases the system once the supply voltage has clearly reached the safe operating range.

Brown-Out Reset (BOR)

While POR takes care of system startup, the Brown-Out Reset (BOR) handles unexpected power drops. In many cases, BOR is even more important than POR when it comes to protecting data integrity.

Imagine an industrial controller writing data to non-volatile memory. Suddenly, a nearby heavy machine turns on and causes about a 20% drop in the main power rail. Without a BOR, the controller would keep trying to write data even though the logic voltage is no longer valid. The result could be a corrupted file system.

Key ASIC’s BOR circuit continuously monitors the 0.8V core domain while the system is running.

• Instant Reaction: If the voltage drops below the safety threshold (triggered by the critical ±7% variance limit), the BOR immediately forces the system into a safe reset state.
• Prevention of Execution Errors: By stopping the processor before the voltage gets low enough to cause logic errors, we make sure no corrupted data is written to memory.

Targeting the 0.8V Core Domain

Designing analog protection circuits for a 0.8V core voltage is quite challenging. At 3.3V, a 100mV fluctuation is usually insignificant. But at 0.8V, a 100mV drop equals about a 12.5% change—large enough to cause timing violations and logic failures.

Key ASIC’s IP is designed for high-precision voltage monitoring:

• Tight Tolerance (±7%): The IP is designed to trigger the reset logic when the voltage deviates by more than about 7% from the nominal 0.8V. This tight window lets designers push their chips closer to the lower edge of the voltage specification for better performance, while still maintaining reliability.
• Low Quiescent Current: Even though the circuit continuously monitors the voltage, it’s optimized for very low power consumption. This makes it well suited for battery-powered IoT devices, where every microamp matters.

Industrial Grade Robustness: -40°C to 85°C

Consumer electronics usually only need to operate between 0°C and 70°C. But the applications targeted by this IP—such as smart meters, factory automation controllers, and automotive infotainment systems—require much tougher operating conditions.

Analog circuits like voltage references and comparators, which are commonly used in POR/BOR designs, are very sensitive to temperature. A threshold that’s set at 25°C can shift quite a bit at higher temperatures. This can lead to false resets (nuisance tripping) or, even worse, a failure to reset during a real fault, which can create safety risks.

To address this, Key ASIC has implemented advanced temperature compensation techniques in the IP:

• Stable Bandgap Reference: The internal voltage reference stays very stable across the full industrial temperature range of –40°C to 85°C.
• Process Compensation: The design is robust against silicon process variations (such as fast and slow corners), ensuring that chips manufactured in different production lots still behave consistently.

Use Cases and Applications

This combined POR/BOR IP serves as a solid foundation for many different types of SoCs:

1. Industrial IoT (IIoT): Devices are often deployed in remote or harsh environments where the power grid may be unstable. The BOR ensures the system resets properly during power fluctuations instead of getting stuck in an unknown state.
2. Solid State Drives (SSD) Controllers: Protecting data during unexpected power loss is critical. A fast-acting BOR helps trigger emergency data-flush procedures to prevent data corruption.
3. Wearables and Medical Devices: These systems often run on ultra-low-power 0.8V cores. Precise voltage monitoring helps manage battery life and ensures the device shuts down safely as the battery drains.
4. Automotive Subsystems: For non-ISO26262 critical systems—such as infotainment or comfort controls—this IP provides reliable operation even in the noisy electrical environment of a vehicle.

When chasing higher performance and lower power, don’t overlook the basics. A solid reset scheme can be the difference between a reliable, industrial-grade product and one that comes back from the field with issues.

Key ASIC’s POR IP for 0.8V cores delivers the precision, temperature stability, and easy integration needed for next-generation designs—keeping your system safe and stable from the very first clock cycle.

【About Key ASIC】

Key ASIC, listed on Bursa Malaysia (0143), is one of the world's leading turnkey ASIC design service companies, offering comprehensive support from design to chip production.

• Over 100 ASIC designs in mass production
• 100% successful ASIC tape out
• Over 150 silicon-proven IPs (e.g., DDR, SerDes, PCIe, USB, Ethernet, etc.)

As a foundry-independent company, we collaborate with top-tier foundries worldwide, providing unparalleled flexibility and expertise to meet our customers' diverse needs.

Key ASIC is here to provide the best partnership for your ASIC business.

Please feel free to contact us via email: This email address is being protected from spambots. You need JavaScript enabled to view it.