Department/Country: Semiconductor & IoT (KL/TWN)

Job Descripton

We're developing deep neural network computing chips and algorithm across several industries. The AI SW Engineer shall be responsible to go over the entire software design flow for the application of Artificial Intelligence from specification definition, design and integration as well as verificationThe scope of work includes but is not limited to:

        •      Technically coordinate, work hand-on on embedded system, firmware and software in the
                development of AI chip

        •      Responsible for firmware and software development of Linux and Android OS

        •      Be able to do programming using C++, python, and others

        •      Familiar with Linux and Android OS and be able to write drivers

        •      Experience in deploying, implementing AI algorithm into ASIC/SoC/FPGA

        •      Familiar with Verilog RTL coding &simulation, FPGA prototyping

        •      Fluent with machine learning framework such as Tensorflow and others.

        •      Able to create AI algorithm based on machine learning framework

        •      Familiar with image processing algorithm, digital signal processing and image pre-processing. 

Desired Skills & Competency Requirement:

        •      Hand-on experience in the design and development of machine learning

        •      Experience in designing artificial intelligence, machine learning, neural network,
               CPU/GPU/DSP-like accelerator or equivalent domain specific ASIC/SoC

        •      Ability to map neural network to custom hardware architecture and design

        •      Programming skills with C, C++, python is a must

        •      Familiarity with AI framework such as Google TensorFlow, Microsoft CNTK and Caffe is an
               added advantage
        •      Basic deep learning, machine learning or any AI algorithm knowledge

Desired Qualifications and Experience:  

        •     BS/MS in Electrical/Electronic Engineering or Computer Engineering required.

        •     At a minimum of 5 years of experience in embedded system design.

        •     Knowledge & experience in the area of artificial intelligence, machine learning, neural network,
              CPU/GPU/DSP-like chip design

* Delegation of duties during absence (indicate position/title): senior engineer

Department/Country: Semiconductor & IoT (KL/TWN)

Job Descripton

Interfacing with the IP design team and 3rd party EDA tool vendors to drive and coordinateInterfacing with the IP design team and 3rd party EDA tool vendors to drive and coordinateeffort of developing and validating simulation flows, enhancing custom design environment,validating checks and doing results analysis.

Key Responsibilities:

        •      IC design background and CAD automation support and development.

        •      Knowledge of the Cadence Virtuoso Design Framework, Virtuoso SchematicEditor, and Analog
               Design Environment (ADE-L/XL/GXL/Explorer/Assembler),including flow automation and
               custom netlisting with SKILL.

        •      Proficiency with digital and mixed signal simulators: Incisive/Xcelium, VCS,AMS Designer,
               CustomSim-VCS, etc.

        •      Strong ability to solve simulation accuracy, speed and capacity issues.

        •      Experience in evaluating simulation and environment related CAD tool/productapplications,
               and driving EDA vendors to meet design requirements.

        •      Very efficient programming skills and good software developmentfundamentals in Python, Perl,
               and SKILL.

        •      Managing and maintenance of SVN database repositories.

Job Descripton

       •      Participate in logic/standard cell layout floor planning and editing from scratch.

       •      Perform logic layout verification (such as DRC, LVS, ANT, ERC & PERC) and
          troubleshootingthe results.

       •      Co-work with coding team to enhance logic layout with automation and integration.

       •      Good hands-on experience in logic layout with understanding of backend structure,techniques
          and place & route concept, as well to have acquired broader knowledge inhandling high voltage
          devices.

       •      Responsible for layout optimization, post layout extraction and parasitic analysis by
          ensuringlogic library meets desired area, performance, and power.

       •      Specific logic layout technical expertise is desired in a broad range of process technologiesfrom
           Bipolar, CMOS, DMOS (BCD) to FinFET advance node.

Requirements:

       •      Junior to intermediate engineer is welcome to apply.

       •      1-3 year(s) of recent, direct working experience in standard cell library layout development.

       •      Must possess at least a Bachelor Degree or above in Engineering.

       •      Familiar with IC design logic layout and backend flow.

       •      Preferably well-versed in layout tools (Cadence-Virtuoso, Synopsys-Custom
          Compiler),verification tools (Calibre, ICV, PVS) and parasitic extraction tools (Calibre-PERC,
          Quantus-QRC, Star-RCXT).

       •      Proficient in UNIX (Linux) platforms.

       •      Can speak Bahasa Malaysia/English/Chinese.

       •      Active learning, taking advice and seeking feedback for personal development.

Job Descripton

       •      Lead the PHY architecture development for PCIe 5.0 and USB4 standards

       •      Defines, Documents and Designs of PHY Architectures

       •      System modeling of PHY with Verilog System integration of PHY with controller

       •      Hands-On Experience in high-speed design building blocks for High-Speed Interfaces,
         SERDES,PLL, CDR, RTL logic design, Synthesis, Physical design, Power analysis and/or
         integrationaspects for IO PHY in SoC

       •      Taped-out in PHY Finfet process

       •      PHY Architecture knowledge needs to span multiple domains (Analog, Digital,
         PlatformElectricals, etc.)

       •      Cross-discipline knowledge in any of these areas, such as Analog integration,
         RTL/SystemVerilog, Static timing analysis concepts, APR, Floor-planning, Metal-routing, Power-
         grid andArchitecture specification documentation.

Key Responsibilities:

       •      Innovate and own System Modeling, Architecture, Design and Development of
         highperformance, low power IO PHY meeting latest USB4 and PCIe 5.0

       •      Owns PHY level Architecture study and recommends system-level design trade-off alignedto
         IP/SoC requirement and roadmap

       •      Collaborate across functional teams - Logic, Circuit, Verification, Structural Design in PHYlevel
         definition meeting Best in Class Power, Performance and Area metrics

       •      Collaborate with SoC integration teams on PHY level requirement and integration issues

       •      Mentor and develop technical leadership

Job Descripton

       •      Participate in sub-blocks and module-blocks floor planning and routing from scratch.

       •      Perform layout blocks verification with sign-off in area (such as DRC, LVS, ANT, ERC &
          PERC)and troubleshooting the results.

       •      Good hands-on experience in analog layout device matching techniques, high speedshielding
          and validation, as well to have acquired broader knowledge in handling highvoltage devices.

       •      Co-work with architect, design lead, designers, layout lead and layout engineers to
          achievemodules/full chip integration, place and route, chip level verification and tape-out.

       •      Responsible for layout optimization, post layout extraction and parasitic analysis by
          ensuringanalog and mixed signals circuits meet chip level tape-out, sign-off at desired
          area,performance, and power.

       •      Specific technical expertise is desired in a broad range of process technologies from
          Bipolar,CMOS, DMOS (BCD) to FinFET advance node in complex, high-performance analog
          andmixed signals circuits layout.

       •      Proactively look for continuous improvement opportunities in the complete layout
          flowmethodologies (flow, layout, and design) as well as develop accurate IC layout
          designschedules and resource estimates.

Requirements:

       •      Degree in Electrical/Electronic Engineering or Micro Electronics/Physics with excellenttechnical
          background in Analog/Mixed Signal IC Design environment.

       •      Senior engineer with 5 to 7 years of job experience in layout design field is preferred.

       •      Hands-on experience in analog layout from scratch for a number of design blocks etc:
              AnalogSwitch/Bandgap/Current Mirrors/Power Management Blocks/Charge-
              Pump/PLL/ADC/DAC/LDO and mixed signals circuits layout experience from scratch for
              PCIe/USB/SATA.

       •      Possess strong technical, analytical and problem-solving skills in physical layout
              developmentwork.

       •      Preferably well-versed in layout tools (Cadence-Virtuoso, Synopsys-Custom
              Compiler),verification tools (Calibre, ICV, PVS) and parasitic extraction tools (Calibre-PERC,
              Quantus-QRC, Star-RCXT).

       •      Preferably experience on Bipolar, CMOS, DMOS (BCD) and FinFET advance technologies.

       •      Comprehensive understanding of the target process to balance layout and design needs,
              e.g.crosstalk, RC delay, electro-migration, IR drop, self-heating, shielding, matching, guard
              ringsand latch-up.

       •      A team player with good communication skill and strong organizational skill as well to
              workindependently.

       •      Proficient in UNIX (Linux) platforms.

       •      Proficiency in PERL, TCL or PHYTON scripting is a plus.

       •      Can speak Bahasa Malaysia/English/Chinese.

       •      Active learning, taking advice and seeking feedback for personal development.

Department/Country: IP team/ KL & Taiwan

Reports To: IP Design Manager

Job Descripton

As senior/staff analog design engineer, this person is required to support all analog design activities on company products, design services, physical design implementation as well as internal IP development. Working closely with other engineering and product marketing teams for end product development. Below are the responsibilities:

       •      Responsible for entire analog design implementation that covers design specification, design
          creation, integration and optimization to layout review, final post-layout simulation, silicon
          characterization and system test and debug.

       •      Experience in analog IP development that include
          ADC, DAC, Audio Codec, PLL, IO, memory, analog blocks and high speed PHY for 130nm,
          90nm and below technologies.

       •      Knowledge in high speed PHY design (PCIE, USB, GbE, DDR) is an added advantage.

       •      Preferably done some test characterization, measurement and compliance in previous
          employment.

       •      Effectively lead the design engineers, if needed and train and guide them technically and to
          achieve common goals.

Desired Skills & Competency Requirement:

       •      Must have in-depth knowledge in circuit and logic IP design flow with hands-on experience in
              design and development, mixed signal design and simulation verification, IP test /                   
              characterization, low power high speed design methodology. Scripting in Perl, TCL, Unix, Linux

       •      The ability to work with multiple team members

Desired Qualifications and Experience:

       •      Min bachelor degree in electronic

       •      Min 5 years’ experience in related field (for senior)

       •      Min 8 years’ experience in related field (for staff)

       •      Working experience in EDA tools such as Synopsys Design Compiler, Physical Compiler,
          PrimeTime etc is a plus.

* Delegation of duties during absence (indicate position/title): Senior Design Engineer

Department/Country: Semiconductor, IoT & AI (KL/TWN)

Job Descripton

Seeking a self-motivated, team-oriented system board design engineer to develop embedded system products. This position requires experience in hardware architecture, sensors interface, signal conditioning and power design. A successful candidate will have a good knowledge of embedded system board design and implementation. In addition, this candidate will have a good working knowledge of signal and power supply design as well as sensor interface, signal amplification, and use of filter and ADC on-board. Experience with PCB design tools (Cadence/Mentor PCB design and analysis). Expertise in design for optimum signal and power integrity as well as hands-on lab measurements experience is a must. Candidate should have a thorough understanding of hardware development methodologies in embedded system products to achieve a first pass design success. The scope of work includes but is not limited to:

•      Interface in cross functional teams to ensure the design meets all firmware, diagnostic and
       system level requirements.

•      Participate in architecture definition and lead designing of embedded system products.
       Complete ownership of hardware through the product life cycle.

•      Perform detailed verification of the design in lab to ascertain the design margins.

•      Document and communicate results with cross functional counterparts.

•      Debug design issues and capture reports.

•      Experience in designing high volume and cost sensitive products (keeping manufacturability
       challenges in mind)

•     PCB back-end process: defining stack-up and via technologies, part placement, setting design
      constraints

•     Works proactively with cross functional team members during design and verification

Desired Skills & Competency Requirement:

        •      Self-motivated. Desire to take on challenges. Result-driven and details oriented.

        •      Strong interpersonal and communication skills are a must.

        •      Good PCB design experience on signals routing guideline and review design for EMI/ESD
               protection.

        •      EVB and portable product schematics, PCB layout design and mass production.(good to have
               various sensor, filter, Wi-Fi design and verification experience)

        •      Had previously completed system and board design for electronics products (added
               advantage)

        •      Experience developing embedded system devices within FDA, ISO, CE, FCC and IEC
               requirements and guidelines including risk analysis and quality assurance. (added advantage)

        •      Fluency with schematic design. Cadence toolsets experience preferred.

        •      Practical experience with design/measurement tools and real time/sampling scopes

        •      Cadence Sigrity, Allegro Power-Aware SI, Mentor Graphics HyperLynx, Altium (will be a plus).
               EMC design/debug and certification (Good to have PI/SI simulation skills).

        •      Basic knowledge of controls, motor and sensors theory with some coding ability (python, java,
               or C++) is an added bonus.

        •     Working knowledge of various standards with regards to PCB manufacturing and assembly
              techniques

        •      Creates moderately complex printed circuit board layouts and documentation from schematics
                using Computer Aided Design (CAD) tools such as Cadence Allegro, Altium, Orcad, Eagle and
                etc.

        •      Support Bill of Material (BOM) development for new and updated schematics

        •      Support Bill of Material (BOM) development for new and updated schematics

        •      Expert at troubleshooting and debugging prototype hardware/software

        •      Strong lab and benchtop skills for hardware bring-up, testing, and characterization. Signal
               measurement and test report delivery.

        •      Expert with analog signal conditioning

        •      Familiarity with EMI reduction PCB design

        •      Expert in electronic component selection 

Desired Qualifications and Experience:  

        •      BS/MS in Electrical/Electronic Engineering or Computer Engineering required.

        •      At a minimum of 3 years of experience in embedded system board design industry

        •      Experience using PCB schematic and layout tools 

Department/Country: IP Team / KL & Taiwan

Reports To: IP Design Manager

Job Descripton

As senior/staff digital design engineer, this person is required to support all digital design activities on company products, design services as well as internal IP development. Below are the responsibilities:

       •      Responsible for RTL Design and writing of test bench

       •      Experience in IP core design such as peripheral interfaces, CPU cores, digital controllers

       •      Architecture review, RTL design, functional verification, post synthesis simulations.

       •      Responsible for SOC system Integration & verification

       •      Experience in SoC Architecture and Microarchitecture A

       •      Experience in ARM CPU integration to SoC

       •      Experience in SDRAM Memory Controller integration

       •      Experience in interconnect matrix, AHB Bus Arbitration, multi-layer AHB Bus architecture

       •      Experience in SoC Peripherals design: GPIO, RTC, UART, I2C, I2S, and SPI

       •      Excellent in Verilog RTL coding and simulation

       •      Familiar with FPGA prototype and verification

       •      SD/SDIO relative experience is an added advantage.

       •      AMBA Interface relative experience is an added advantage.

       •      Knowledge in controller design (USB, PCIe, SATA, and Ethernet) is an added advantage.

       •      Preferably done some FPGA prototyping in previous employment

Desired Skills & Competency Requirement:

       •      Verilog RTL coding- Verilog RTL coding

       •      SoC design flow and SoC peripheral IP design

       •      FPGA prototyping and emulation

       •      System validation and verification

       •      Characterization and the handling of test equipment

       •      Digital front-end design, simulation and synthesis

       •      Verification in system Verilog OVM

       •      Low power synthesis methodology

       •      Digital support on DFT and ATPG

       •      Scripting in Perl, Python, TCL, UNIX, Linux

Desired Qualifications and Experience:

       •      Min bachelor degree in electronic or IT

       •      Min 5 years’ experience in related field (for senior)

       •      Min 8 years’ experience in related field (for staff)

Location: Taiwan

Job Descripton

       •      Supervise system engineering div. to instruct and guide members successfully completing 
          assigned engineering works within preset time line

       •      Organize and plan 3 yrs man power requirement to fulfill company KPI.

       •      Pick up core technologies from R&D div. to create various system level products according to
          market/customers demand, covering HW, SW and testing working scopes to transfer the design
          over to customers for mass production.

       •      Allocate resources to fix system related issues on time.

       •      Communicate with R&D supervisor to resolve cross over engineering issues.

       •      Report working progress to management regularly.

Desired Skills & Competency Requirement:

       •      Strong ARM9 platform HW and SW( BSP ) development capability.

       •      SD & SDIO controller driver porting and debug experience.

       •      WiFi driver porting and debug experience.

       •      Quick reaction for trouble-shooting technical issues

       •      Lead-ship

       •      Learn and utilize new technologies quickly

Desired Qualifications and Experience:

       •      MSEE or BSEE

       •      10 years or above system engineering working experience in IC design company

       •      Tracked record to lead team for developing system solutions.

       •      8 years or above design career out of total working seniority.

Location: Taiwan

Job Descripton

       •      Responsible for system product and chip production

       •      Production SOP and ISO implementation and control

       •      Operation (PE/TE/QRE/PC/MM/Lab) related SOP setup

       •      Document control center

       •      Production / Quality system setup/Yield Improvement, Reliability Assurance

       •      New project evaluation and quotation.

       •      ASIC turnkey projects

       •      Annual planning / Rolling forecast

       •      Semiconductor Subcontractors management (MASK, foundry, assembly, testing, warehouse)

       •      System Product contractors management (EMS, OEM, ODM)

       •      RMA/Maverick lots analysis and disposition

       •      Acting as Head of Purchasing-Vendors identification and selection, Sourcing and Price
         negotiation

       •      Continuous cost improvement – purchasing capability, sourcing and productivity improvement.

       •      Inventory / WIP management

       •      Import / Export / Forwarder solution

       •      Lab management

       •      Lab Outsourcing activities management

Desired Skills & Competency Requirement:

The candidate must be

       •      Excellent production planning and scheduling skill.  Hand on experience in ERP system
         establishment and support will be added advantage.

       •      General System Products and Semiconductor manufacturing process.   Experience in foundry
         or semiconductor, EMS, OEM, ODM, subcontractor management is a must.

       •      Supervisory and management skill

       •      Able to work with communicate effectively internally and externally.

       •      Effective negotiation skill

Desired Qualifications and Experience:

       •     Bachelor degree in Engineering, Science (major in Electronics), Operation and logistics
         management, Business administration.

       •     Degree in other field could be considered based on work experience or supplement with post
         graduate study in the related field.

       •     The suitable candidate must have at least 5 years of working experience in Semiconductor
         industry.

       •     In addition, the candidate must also possesses supervisory and management experience

Department/Country: Sales & Marketing
Reports To: CEO

Job Descripton

The primary responsibility is to develop and grow new business in US and Europe for turnkey ASIC designThe primary responsibility is to develop and grow new business in US and Europe for turnkey ASIC designservices as well as System solution sales. The customers are fabless IC design companies, system companieswith ASIC design primarily in the space of consumer electronics and communication products. You arerequired to be responsible for sales target and expect to achieve or exceed the target. Developing newcustomers, ensuring customer success and expanding customer into major accounts are primary goals. Youare responsible for design wins, delivery and customer management.

Responsibilities:

       •      Achieve or exceed annual sales targets set while maintaining profitability.

       •      Promote and market ASIC design services

       •      Promote and market System solution sales that includes:
              - SPG101 chip
              - Mcard and Mdrive
              - AI chips
              - Medical AI products

       •      Work with various internal teams to carry out strategic marketing plans to gain market share.

       •      To develop marketing strategies and materials for sales & marketing campaigns and 
              promotions.

       •      Keep detailed records of all contacts and engagements.

       •      Organize and participate in client networking sessions to develop the Company and client
               workingrelationship.

       •      Organize events, seminars and conferences to evangelize the market.

       •      Any other duties as assigned.

Desired Skills & Competency Requirement:

The ideal candidate will have a minimum of 3 years of sales experience in the semiconductor, ASIC designThe ideal candidate will have a minimum of 3 years of sales experience in the semiconductor, ASIC designbusiness or EDA industry. One needs to familiar with the ASIC/COT design flow, knowledgeable inManufacturing, testing and packaging. This position needs to be very familiar with the outsourcing model ofsemiconductor business. Knowledgeable and working experience in specific application segments of theconsumer and communication chips is required. Exceptional knowledge and experience of all aspects in chipdesign and production is a plus. The ability to work with and develop relationships with multiple functiongroups and execute in a fast paced environment is essential. Good sales track record is a must.

Desired Qualifications and Experience:  

       •      BS in Electrical Engineering or Computer Science required, with an MBA preferred.

       •      At least 3-5 years of business development, marketing, and/or sales experience.

       •      Engineers and FAEs with good sales exposure shall be considered also.

       •      Experience marketing or selling products or services in a start-up or early stage environment.

       •      A solid understanding of company’s market: products, players, technologies, and contacts in
              related markets.

* Delegation of duties during absence (indicate position/title): CEO

Location: Shanghai

Job Descripton

       •      The primary responsibility is to develop new customers in China or Asia for turnkey ASIC
          design business.

       •      The customers are fabless IC design companies, system companies with ASIC design primarily
          in the space of consumer electronics and communication products.

       •      You are required to be responsible for sales target and expect to achieve or exceed the target.

       •      Developing new customers, ensuring customer success and expanding customer into major
          accounts are primary goals.

       •      You are responsible for design wins, delivery and customer management.

Desired Skills & Competency Requirement:

       •      One needs to familiar with the ASIC/COT design flow, knowledgeable in Manufacturing, testing
          and packaging.

       •      This position needs to be very familiar with the outsourcing model of semiconductor business.

       •      Knowledgeable and working experience in specific application segments of the consumer and
          communication chips is required.

       •      Exceptional knowledge and experience of all aspects in chip design and production is a plus.

       •      The ability to work with and develop relationships with multiple function groups and execute in a
          fast-paced environment is essential.

       •      Good sales track record is a must.

Desired Qualifications and Experience:

       •     The ideal candidate will have a minimum of 3 years of sales experience in the semiconductor,
          ASIC design business or EDA industry.