DFT/Senior DFT (Design-For-Testability) Engineer

  • DFT/Senior DFT (Design-For-Testability) Engineer

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Job Description:

In this position, you will be responsible for all the DFT related matters in the design. Your scope of work includes but not limited to
• Perform DFT logic insertion and stitching into the RTL codes or netlist using CAD tools, which includes ATPG scan (internal/compressed stuck-at and at-speed scan), Memory BIST and Boundary Scan
• Work closely with front end team to ensure the logic structures permit/are suitable for DFT insertion
• Work closely with front end/customers and back end team to make sure the DFT implementation does not impact the functionality and timing of the chip 
• Develop the timing constraint files for DFT corners
• Perform STA and drive for timing closure in DFT corners
• Develop DFT test benches
• Perform gate-level simulation to ensure the post-layout design passed the DFT test benches
• Prepare DFT test patterns for production team
• Develop DFT methodology to improve runtime and design testability
• Perform DFT sign-off checklist and reviews

Limited Requirement

DEGREE:
BS/MS in Electrical/Electronics/Computing Engineering required. Previous experience in DFT is a must. Advanced degree in an engineering discipline is a plus.
Other Requirement:
The ideal candidate should have at least 3 years of experience in related field for senior level, and minimum 1 year of experience for junior level.
The candidate should have strong knowledge in scan, mbist and boundary scan concepts, with hands-on experience in the insertion of DFT logics, test pattern generations, test benches preparation and post-layout verification with SDF annotation. Hands on experience in OCC (on-chip clocking) scan insertion for multiple clock domain at-speed scan is a must. The candidate needs to be able to work independently on all the tasks (minimal guidance for junior level). In addition to that, he/she needs to have general knowledge in all aspects of the ASIC design flow. Hands-on experience in physical implementation flows like RTL synthesis, place & route, static timing analysis and timing convergence skills is a plus. The ability to work with and develop relationships with multiple function groups and execute in a fast paced environment is essential. 
We are looking for independent, energetic, dynamic, proactive and responsible person to fill this position. 

 

Post Date:2014-10-27