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  • info@keyasic.com
  • Petaling Jaya, Selangor Darul Ehsan, Malaysia

32-bit ARM926EJS

KeyASIC SPG series microcontroller is a system-in-package (SiP) SoC based on ARM926EJS core that support extremely wide range of application. It is highly deployed in telecommunications, industrial and control applications. Running at a clock rate of 200MHz, this microcontroller is an entry point processor capable of supporting a full operating system and multi-tasking application. It features rich connectivity peripherals, high data bandwidth architecture, and a small footprint package option, making it an optimized solution for industrial applications. One thing worth mentioning is, besides the rich peripherals interface for typical embedded system, this microcontroller also contains built-in memory, and offer options to add external FLASH memory via SD bus, and external I/O devices via SDIO bus. Wireless connectivity modules such as Wi-FI, Bluetooth, 2G/3G sim card and others are seamlessly integrate-able with SPG microcontroller with these available interfaces. Together with its patented proprietary SD switch, SPG SoC is able to dynamically switch between request coming from wireless transmission interface and SD interface. When data is stored into the FLASH, it can also be wirelessly transmitted out (read) or written in (write) through the connectivity module, thus acting as a device that makes things IoT-connected.

Area of application

●     Industrial machinery

●     Factory automation

●     Telecommunications

●     VoIP, Ethernet, power line communication

●     Industrial monitoring, metering and control

●     Display & touch-screen

●     Consumer electronics

●     Automotive

●     Medical & healthcare equipment

●     Internet of Things (IoT)

Key Features

ARM926EJS

● 200MHz

● 16KB I-Cache

● 16KB D-Cache

● 200 MIPS of computing power

● Support 16/32-Bit instruction sets

● MMU enabled

● Little Endian default

 

Internal Bus (Advanced Microcontroller Bus Architecture) (AMBA2.0, AHB/APB)

● 3 AHB (Advanced High-performance Bus)

● 1 APB (Advanced Peripheral Bus)

 

System Operating Clock

● On-chip PLL 100 ~ 300MHz

● Clock reset generator to generate system clock and reset

 

SDRAM Controller

● Supports up to 32MBytes of external SDRAM

● Support self-refresh mode

● Single-chip SDRAM up to 100MHz

 

JTAG

● For the purpose of ARM926EJS debugging

 

Interrupt Controller

● Support up to 64 interrupts

 

Auto-load Flash Controller for NOR Flash

● SPI Flash support up to 8Mbytes of NOR

● AHB master interface for data transfer

 

SPI Master interface for read/write NOR-flash

 

SD Master interface

● Support SD 2.0 (SDHC)

● Support bus width of 1 and 4-bit

● AHB master interface for data transfer (DMA)

● APB interface for software programming

 

SD Slave interface

● Support SD 2.0 (SDHC)

● Support iSDIO commands (CMD48/CMD49)

● Support user-defined commands

● AHB master interface for data transfer (DMA)

● APB interface for software programming

 

SDIO

● Support SDIO 2.0

● Support bus width of 1 and 4-bit

● AHB master interface for data transfer (DMA)

● APB interface for software programming

 

Pulse Width Modulation (PWM) and Timer

● APB interface.

● One 16-bit timers with PWM support

● Two 16-bit generic timers with interrupt based operation

● Two 8-bit prescalers & three 2-bit divider

● Programmable duty control of output waveform (PWM)

● Auto-reload mode or one-shot pulse mode

 

Watch Dog Timer

● APB interface

● Internal reset signal is activated for 128 PCLK when the timer counts until 0

● Normal interval timer mode with interrupt request

● Switchable between watchdog timer mode and normal timer mode.

 

16 GPIO ports

● APB interface

● Fully configurable 16 GPIO ports

● Bit masking in both read and write operations

● Hardware control capability of GPIO lines

● Programmable Interrupt

● Individually programmable input/output pins

 

Universal Asynchronous Receiver/Transmitter (UART)

● APB interface

● FIFO only operation

● Register level and functionality compatibility with NS16550A (but not 16450)

 

Serial Peripheral Interface (SPI)

● 32-bit shift register data for transmitting

● 32-bit shift register data for receiving

● 8-bit pre-scaler for serial transfer baud rate adjustment

● MSB/LSB first transfer selection

● Polling and Interrupt transfer mode

● Master/Slave selection

● Clock polarity selection

● Clock phase selection

● Chip select active level selection

● In Master mode, multi master error detect enable/disable

● In Master mode, serial data out keep/release selection

 

I2C Interface

● Support Master/Slave

● APB interface for software programming

Power Management - CPU Speed Mode
  1. Sleep mode (CPU shutdown)
  1. Slow mode (CPU at external crystal clock frequency 24MHz)
  1. Normal mode (CPU at up to 200MHz)
Package
  1. BGA-144

  2. QFP-208