IP Solutions | Browse IP by Function

 

Key ASIC provides value-added Intellectual Property (IP) libraries to facilitate customer's ASIC / SOC development and meet their application needs, as well as shorten the product's time-to-market.

 

monclova
Low Power Standard Cells

 

Description

This Low Power Standard Cells library using the MCL approach is optimized for Silterra 130nm G process for the wearable, mobile and IOT products. It enables ASIC designers to achieve the power goal easily without changing of the process technology, design flow and redesign of the analog and harden IPs. This library can be used for the entire chip or it can also be used together with other existing libraries of the same process technology to provide the most optimal power. Design can be synthesized fully using MonclovaTM or through substitution of the cells from MonclovaTM wholly or partially. The library has demonstrated average power reduction of 30%-50% generally while optimizing for the performance and area efficiency.


Features

Silterra 0.13umG process
Layer of metal 5, 6, 7, 8
Over 500+ standard cells
9-track with cell height 3.69um
Power and GND routing rail 0.5um
1.2V ±10% Core Power Supply
-40~125C operating junction temperature

EDA Deliverables
FE simulation model - Verilog
BE physical layout - GDSII
BE P&R model - LEF
BE P&R timing model - CLF
Synthesis model – Prime Time & Design compiler
SPICE model (post-layout)
Command file – DRC & LVS
Document – Databook & Integration guide

 

ARM9 Harden Macro Core

ARM9 Harden Core - SoCs for .13u CMOS

Description
With Key ASIC IP and Silterra CL130G process technology,  your designs will achieve the highest performance and lowest cost in the industry. Key ASIC’s portfolio of silicon verified IP provides all of the IO, CPU, and analog functions required for your next multimedia or wireless design.
Features
a) Supports 1.8 volt, 2.5 volt and 3.3 volt interfaces.
b) Single polysilicon layer and up to eight (8) layers of metal.
c) Gate delays: 20ps nom.
d) Compilable single port, dual port, ROM and register files.
e) Flexible IO rings ~ inline and standard.
f) Low jitter PLL and DLL solutions.
g) Industry standard logical libraries.
h) Verified IP Iibraries for consumer and wireless applications.
i) Leading high performance interfaces including PCI Express and Serial ATA.
j) High performance ARM926 & ARM946 available
 
 

 


ARM9 Harden Core - SoCs for .18u CMOS

Description
With Key ASIC IP and Silterra CL180G process technology, your designs will achieve highest performance and lowest cost in the industry. Key ASIC’s portfolio of silicon verified IP provides all the IO, CPU, and analog functions required inyour next multimedia or wireless design requirements. 
 
Features
a) Supports 1.8v and 3.3v supplies.
b) Single poly, up to 6 layers metal.
c) Gate delays: 25ps nom.
d) Compilable 1 port, dual port, ROM and register files.
e) Flexible IO rings (inline, staggered).
f) Low jitter PLL and DLL
g) Industry standard standard cell libraries.
h) Verified IP Iibraries for consumer and  wireless applications.
i) 1.8 / 3.3 volt options.
 


KA IP List By Function

Primitive IP
IP Part NumberCategory (Analog, or Mixed Signal)Function DescriptionFoundryProcess
KA16UGOSC01ST001 Mixed signal Build in OSC
35M / 50MHz
Trimmable
Silterra 0.16um
KA16UHOSC01ST001 Mixed signal Build in OSC
20MHz
Trimmable
Silterra 0.16um
KA18UGPLL01ST001 Mixed signal PLL
Fin: 10~40MHz
Fout: 100~300MHz
Silterra 0.18um
KA16UGPLL01ST001 Mixed signal PLL
Fin: 10~40MHz
Fout: 100~300MHz
Silterra 0.16um
KA13UGPLL01ST001 Mixed signal PLL
Fin: 10~40MHz
Fout: 100~600MHz
Silterra 0.13um
KA18UGLDO01ST001 Analog LDO
3.3V to 1.8V
Driving: 60mA
Silterra 0.18um
KA16UGLDO01ST001 Analog LDO
3.3V to 1.8V
Driving: 60mA
Silterra 0.16um
KA13UGLDO03ST001 Analog LDO
3.3V to 1.2V
Driving: 60mA
Silterra 0.13um
KA16UHLDO01ST001 Analog LDO
3.3V to 1.8V
Driving: 100mA
Silterra 0.16um
KA16UGLDO02ST001 Analog Cap-free LDO
Driving: 30mA
Silterra 0.16um
KA16UGLVD01ST001 Analog Low voltage detect
Detect: 3.3V
Silterra 0.16um

IO Function IP
IP Part NumberCategory (Analog, or Mixed Signal)Function DescriptionFoundryProcess
KA13UGCUPP5ST001 IO CUP IO - Phase 5 Silterra 0.13um
KA13UGCUPP4ST001 IO CUP IO - Phase 4 Silterra 0.13um
KA13UGCUPP3ST001 IO CUP IO - Phase 3 Silterra 0.13um

ADC/DAC IP
IP Part NumberCategory (Analog, or Mixed Signal)Function DescriptionFoundryProcess
KA18UGDAC01ST001 Mixed signal 8-bit DAC
Conversion rate: 13.5MSPS
Silterra 0.18um
KA16UGDAC01ST001 Mixed signal 8-bit DAC
Conversion rate: 13.5MSPS
Silterra 0.16um
KA18UGDAC02ST001 Mixed signal 8-bit DAC
Conversion rate: 1MSPS
Silterra 0.18um
KA18UGAFE03ST001 Mixed signal Analog Front End
10-bit Pipe line ADC
Silterra 0.18um
KA18UGADC01ST001 Mixed signal 10-bit SAR ADC
Conversion rate: 800KSPS
Silterra 0.18um
KA16UGADC01ST001 Mixed signal 10-bit SAR ADC
Conversion rate: 800KSPS
Silterra 0.16um

Digital IP
Application / PNFunction
Bus interface PCIe 2.0 Controller, PCIE_SIG association compliance
SoC (Digital Photo Frame, Mobile applications, Digital Still camera) JPEG (w / AHB)
SoC (Digital Photo Frame, Mobile applications) LCD Controller
SoC (Card reader) SDController 2.0
TV application TV decoder
SoC SDRAM controller
SoC SPI NOR flash controller
SoC PWM
SoC SRAM controller
SoC Interrupt controller
SoC I 2C
SoC I2S
SoC UART
SoC RTC
SoC GPIO
SoC WDT
SoC SPI
SoC GDMA
SoC SDIO Host Controller
SoC NAND Flash controller
SoC Tcon for analog small panel
KA13ARM92616 ARM 926 / 16K cache .13u
KA13ARM94616 ARM 946 / 16K cache .13u
KA18ARM92632 ARM 926 .18u
KA18ARM94616 ARM 946 .18u